Intel’s Tri-gate: 3D or not 3D, that is the question
A while back there was a flurry of articles discussing Intel’s 3D Tri-gate and 3D technology involving the use of multiple layers of transistors, not just the single layer used today. This “conversation” appeared to have origins around this
discussion of the possible use of FinFET transistors, such as Intel’s Tri-gate at nodes below 22 nm. While there was some interesting stuff in the earlier articles the discussion become a bit frayed around the edges towards the end. This article in Computerworld even threw Multi-Chip Packaging technology into the fray. In the end it appeared this thread had run its course.
Then this article, highlighting the comments of Morgan Stanley analyst Atif Malik, appeared in Barron’s on Monday. The Barron’s article mentions “Intel is leading the way to three-dimensional chip structures” and “Malik expects foundries such as Taiwan Semiconductor Manufacturing and others to quickly follow Intel into 3D circuitry”.
As in many stories we have to go back before we can move forward. The existing CMOS transistor paradigm could be generally described as two dimensional, where the channel, source and drain are all formed within the planar structure of the silicon wafer. If you were able to look at a wafer after the formation of the above, yet prior to the formation of the gate structure, the substrate would be flat or planar.
Now, if you looked at a wafer destined for Tri-gate transistors, at roughly the same stage, you would see elongated rectangles on top of the silicon substrate. In this case the channel, source and drain are all formed within these rectangles of silicon that rise above the planar substrate. One might consider the transistor extends into the third dimension and voila 3D technology … or at least on the transistor level. However, there is still a single layer of transistors and once the passivation is laid down on the finished transistors the chip structure would look similar to current devices. Tri-gate is a transistor structure designed to address leakage problems at the 22 nm process node and below. It is not a chip structure.
So to use a phrase from a old TV crime show, the name of which escapes me, “Let’s be careful out there”.