Ramtron has been working on RFID based products implementing FRAM for a number of years now.  It was during this time that presentations and or conference calls started making reference to a lower power FRAM that was emerging from the work in RFID.  It was further mentioned these developments could be applied to non-RFID devices.  The technical details were however understandably scarce.

So what are the details?

As a very general statement any developments in semiconductors can be attributed to either process/ structure or circuit design.  The same might be anticipated for FRAM.  In this week’s Press Release Ramtron indicated  “The fast write ability of nonvolatile FRAM combined with an innovative IC design has enabled us to achieve the lowest energy consumption …”.  Thus, it sounds this development is probably largely associated with circuit design. Use of the word “innovative” supports the notion that we should see the details in patent documents.

Somewhat coincidentally, four patent applications assigned to Ramtron, relating to the use of FRAM in an RFID system were recently published by the USPTO.  It has been a while since we have seen any patent filings from Ramtron, so it will be interesting to dig into these and, for sure, forth coming publications to generally gain insights into their RFID efforts and specifically the circuit designs behind their advances in low power.

To say I have read a few articles on Apple’s, first rumoured and then confirmed, acquisition of Anobit is an understatement.  Of course not all of the articles were created equal.  Without dwelling on the negative Anandtech provided the most compelling article.  There were numerous interesting points raised.

They differentiated the iOS product line from the OSX line.  While in many ways this seems like a natural demarcation you would certainly not guess it from much of the coverage.  There were some articles stating Apple used Anobit controllers for the MacBook Air while showing an ifixit photo of an Air Flash memory board.  In this iFixit photo one clearly sees Toshiba Flash and a Toshiba controller.  Oh well, but I digress.

It is almost certain an Anobit controller IP block is included in the A5.  The iOS devices fit right into the end use space that might include lower grade Flash.  As noted in the article I co-authored last April there was certainly more than enough real-estate to accommodate such a block.  Further, there was no stand alone controller found on the iPad 2 logic board (step 13). iOS is covered.

What about OSX devices?  Let’s think about them a bit more as it leads down an interesting path.  We know OSX devices, currently represented by the Air, use stand-alone Flash controllers, evidenced by the above iFixit photo.  It is less clear whether Apple will fabricate a stand-alone flash controller for the OSX line.  It could be argued the numbers are less compelling for OSX devices as for iOS devices.  At the moment it is only the, albeit well selling, Air that needs such a controller.  On the flip side this acquisition may foreshadow the expansion of SSD’s in OSX laptops. Additionally,  if forthcoming iterations of Anobit technology are as good as one might guess from the acquisition price, Apple may find it compelling to expand their semiconductor efforts in this direction.

Now comes the deja vu.  This all seems a lot like the Intrinsity acquisition.  In both cases Apple likely non-exclusively used or had access to the technology and liked it.  It is however probably forthcoming iterations for which Apple wants exclusively, possibly even the controller block in the forthcoming A6. In the end we can look back to Steve’s “further differentiate our products” comment at the time of the PA Semi acquisition when thinking where Apple will take Anobit.

At its most fundamental a patent is a bargain between the state and an inventor, where the state receives an enabling disclosure of the invention in return for a limited monopoly.  The state enters this bargain to provide the  disclosed information to the public for the benefit of further invention and building of the next generation of technology.  Over the span of three articles; Cheaper High- … (Suntech),  How BP Blew … (BP), and Advance Could … (GT) Technology Review has unwittingly presented an interesting case study of this bargain in operation.

First, let’s explore the technology in a bit more detail.  In both the Suntech and BP articles there are bits and pieces referring to the work of Schmid at Crystal Systems.  Digging back through US patents to Schmid we find 3,898,051 (‘051), detailing a system and method for growing a crystal.  The charge or feedstock material is contained within a crucible, which is itself contained within a cylindrical resistance heater.  The system further includes a heat exchanger located under the bottom center of the crucible.  It is indicated that a seed crystal may or may not be used, where the seed, if used, would be placed above the heat exchange unit.  As presented roughly in columns four and five of the description the heat exchanger is initially used to ensure at least a portion of the seed crystal remains solid during melting of the charge.  As disclosed, initial crystal growth begins with increased gas flow rate to the heat exchanger i.e. increasing the amount of material with a temperature below the melting temperature.  At a point later in the growth cycle the temperature of the crucible side walls is also lowered to further crystal growth.  The first example of ‘051 details the growth of a sapphire crystal.  At the moment I do not want to argue whether the detailed system and method outlined in ‘051 worked for the growth of a silicon single crystal.  For the sake of the current article let us assume this is the “first generation” technology for silicon crystal growth that in fact provided multi-crystalline structures when used according to the disclosed embodiments.

Back to the bargain.  The ‘051 patent expired in the early ‘90s and come the turn of the century there is renewed interest in solar power.  Particular interest in systems and methods of reducing the production costs of the single or mono-crystalline silicon active material.  With the assumption that the ‘051 system did not work for silicon, what might be improved, or how might the base process be modified to yield better results for Si? In general one wants to promote the growth of a single, oriented, crystal while mitigating or at least controlling nucleation and growth of “secondary” grains. The nature of the seed crystal and the location, amount and nature of heat flow from the charge during crystal growth are two parameters that come to mind for tinkering.

In the above articles we are introduced to various inventors and/ or assignees including Nathan Stoddard, GT Advanced Technologies and Suntech.  With reasonably straight forward searches USP 8,048,221 (‘221) to Stoddard and US patent application 12/999,439 (‘439) assigned to GT Solar came to light.  No published documents assigned to Suntech that appeared related to their work in the area were found, suggesting any related patent applications are still in the 18 month pre-publication window.  We do however have published images of silicon that purportedly results from their casting process.

From the above we do in fact see work around the number and nature of seed crystals and the nature of heat flow from the furnace.  With regard to seeds both a single and multiple seeds are disclosed.  In a case of more than one seed the seeds may be tiled into a specific pattern on at least one surface of the crucible.  With regard to heat flow, there are examples where heat input or extraction is a function of the particular surface in the furnace and another case where  the furnace insulation is movable to control heat flow from the crucible.  With regard to the Suntech process we will be looking for correlation between any disclosed information in patent documents and the observed microstructure.

There is much more that could be said about the current crop of casting technologies.  That though is for another forum. It would also be interesting to consider if the technologies can co-exist,  i.e. what are the freedom to operate considerations for the second generation and where further patent data points might fall if and when patent coverage around the casting technologies is expanded.  With regard to the US patents that are now beginning to emerge it may ultimately be qualified US attorneys that opine on the various issued claims, and if there is room for all of these second generation casting technologies to operate freely.

“I don’t get no respect” … was that Rodney Dangerfield or technology?

While this was of course Rodney Dangerfield’s classic tag line, it could have easily been technology’s.  With so much of today’s world somehow touched by technology it is sad it does in fact get so little respect.  There is a very historical approach to technology insights with the writing containing portions of entertainment and fairy dust.  We all remember the mythical under the covers Popular Science article about flying cars.  Coverage of the development in polarized optical converters at which we have looked draws on some of the same inspiration, with the entertainment bits detailing Superman’s memory crystal taking up plenty of words of the various articles.  Unfortunately these entertainment bits have the longest retention of all the presented information.  It does not have to be this way.  Technology can be approached with interest and excitement, while keeping it in context and giving it a little respect.

So how do you give technology respect? The key is presenting no more and no less.  Discuss the development, accurately and with honesty.  The interest should come with the understanding of how the subject technology advances a long standing problem or overcomes a hurdle in its field.  To this end it is important to put the technology in context.  Once contextualized it can be appreciated in the broader field where it finds itself.  The technology can stand on its own with the knowledge of how it fits in the world, without the need for an entertaining angle or extrapolation to support it.

Now, what about polarized optical converters?  Interest in this development is at least in part because of the storage medium.  Glass would seem pretty high up there in terms of the hierarchy of media.  It is physically and chemical stability, it is simple, and assuming no funky additives or coatings it is environmentally benign.  These very characteristics do however make glass difficult to manipulate. There has been previous work on the storage of information within glass, including work with holograms in Japan around 2005.   Beyond the basic storage mechanism there is for sure much engineering work ahead.  The targeted data archiving applications are probably reachable first, and any extrapolation to consumer markets further down the road.  Yes, there is a long ways to go, but you have to start somewhere.  The simple notion that two states can be written into glass on a scale suitable for data storage warrants our attention and  respect.

No pun intended, but thermostats do not traditionally fall into the cool category.  Then there was Nest.  Despite not having any buttons the nest thermostat seems to push all the right ones;  slick stripped down industrial design, a nod to nostalgia for the round analogue thermostats of days gone by, and recognition of the annoyances of the poorly thought out menus and programming sequences one often finds in traditional programmable household thermostats.  To top it off, if there were not already enough things to catch your attention, the projected possible energy savings are impressive.

With its bent on minimalist industrial design it is no surprise nest’s founders include Apple alumni.  With such pedigree it would also not be a surprise if there is significant technological innovation below this minimalist skin.  But is there patentable subject matter here? A few quick assignee and inventor searches of the USPTO databases did not find any published documents.  Not to worry.  It is still rather early since the systems and methods were likely scoped out.  In terms of this article this is a good thing as one now has the freedom to conduct a thought experiment considering where inventive material might be found.  In doing this experiment it is noted that I am not frequent with any such filings or the art around thermostats.

In terms of hardware there is likely a micro-controller with embedded memory for code, maybe some stand-alone memory such as BBSRAM, the sensors and communications integrated circuits.  At first glance this seems to be a pretty standard kit for data collection and control.  While the broadest combination of these parts might not present much novelty, there might be some in a particular configuration of parts or systems in this application.

What about software or methods of operation?  Similar to the old analogue thermostats the nest thermostat takes a minimum of inputs.  Two to be exact, a heat to temperature  and a cool to temperature.  Once these are entered the thermostat learns, which is where it becomes interesting.  One might envision “A System and Method for Controlling Temperature” incorporating the two temperature settings and data collected during operation thereof.  Going a bit further one can hypothesize steps of “collecting light level data”, “collecting motion data”, “determining current time”, “recalling a heat to temperature” and maybe a decision loop “determining if the light level data is below the average light level during a first time interval”, and “if yes and time is after a first night time then drop the temperature 10 degrees below the heat to temperature” … or something like that.

Time will tell what, if any, patent applications have been filed.  Whether nest envisions itself as a stand alone company with possibly a family of like minded controllers or as an IP portfolio for an established player in the field, patents can only be seen as essential to protect any novelty residing behind that round display.

OK I’m back.  Thinking back to Part I, terms such as whirlpools, vortexes and 5-dimensional memory are all part of the jargon based noise obscuring an understanding of the key technological development.  In the most basic terms the ability to store data is the ability to store 1’s and 0’s.  More generally it is the ability of the storage medium to be in either a first state or a second state.  As is illustrated in Fig. 5 of the APL paper, reproduced below, a first and second state provide for a different sense of light polarization.  While there are many different parameters, or performance criteria that would need to be considered in a practical application the root is the above ability.  Extending from this basic concept, there are several technical questions left hanging after the four articles in question.  The ability to erase and re-write data, and the ability to bring a data storage system to a consumer application are two that will be considered here.

(source: Appl. Phys. Lett. 98, 2011001)

We are presented by bits of information related to the nature of data storage.  In particular what is occurring on the atomic or near atomic level that allows for information storage?  A few excerpts: “… lasers to create sub-wavelength anisotropic modifications in silica glass” (APL); “… ultrashort lasers can be used to imprint tiny dots called voxels on glass.” (Southampton); and “… the process makes the glass slightly opaque and polarizes the light” (Telegraph).  Again the APL paper probably provides all the best  information.  Subsequent descriptions largely muddy the water.

If we are simply aiming for a read only memory we do not really need to know the mechanism of manipulation within the glass.  One might postulate that data archiving applications do not necessarily require the rewriting of data.  It would certainly be an asset, but its absence might not be a show-stopper.  However, as other applications creep into the story we would like more information about the write and more particularly the re-write mechanism.  How is the glass altered by the laser?  Is the volume of material crystallized? Is the distribution of network modifiers in the glass altered?  We do not know at this stage.  It is particularly not clear to this author how you can manipulate a volume of atoms within glass such that the original manipulation is reversed.  Maybe you never actually return to the original state of the glass for a re-write.  Maybe the write process is independent of the volume’s original state.  Further, with the storage mechanism requiring the transmission of light through the glass there can only be one bit along a given optical path.  That said one could envision algorithms that guide the writing of data to “virgin” material.  Maybe the initial write is deep in the thickness of the glass and subsequent writes are higher up, as the optical detector is one the same side of the storage medium as the laser.  The “level” being identified in some record whose location is constant.

The commercialization of this technology is another matter.  Some details around the experimental set-up presented in the APL paper suggest there is a ways to go before any end products appear.  Namely, the APL paper notes “The stages (holding the glass sample) were computer controlled … to move in a spiral trajectory with steps of 1 micron, enabling in a complete scan to cover uniformly a circular area of 1.2 mm diameter in about 1.5 h.”  A few questions that arise include data transfer rate, power consumption, laser power and size.  While the Telegraph article indicates the authors have refined the techniques since the APL paper there appear to be orders of magnitude of improvement required in parameters such as write time.

In the end there is plenty of interesting stuff in this development, including the ability to create a volume of glass that alters the polarization of light, on a scale that may prove useful in data storage applications.  While the development is real and deserves respect it is certainly at the beginning of the commercialization path.  After reading the four articles one is left with some real technical questions, whose answer will determine the acceptance of the technology.  It is also the case that the three articles after the original APL paper present unreal expectations that only trivialize the technology.  It is only once these are peeled away the original development can be considered on its merits.

Published United States Patent Application 2011/0221575 (‘575) came to light last week catching the attention of Appleinsider.  The timing of such publications is often an interesting coincidence, with ‘575 appearing just as rumours say iPhone 5 is about to arrive.  Will iPhone 5 have RFID capabilities?  It is certainly too big a leap to think the iPhone 5 will sport RFID capabilities because of this application.  However, there were some interesting hardware considerations in the various embodiments discussed in ‘575.

In broad brush strokes ‘575 presents systems and methods for providing messages related to the operation or failure of an electronic device, even after the device has failed.  These messages may include error messages and messages related to the operation of software on the device.  RFID circuitry is well suited to this use as it can be independently powered by the RF reader allowing information be extracted from the RFID memory, even after the rest of the device, including the power supply, has failed.

Embodiments of an RFID system are outlined in Fig. 3 and Fig. 4, and discussed in paragraphs [0026] to [0029], and [0030] to [0032], respectively.  In both embodiments specific error messages are stored in separate pre-programmed memories, with the system in Fig.4 having a higher granularity.  In both of these embodiments a particular error message is stored in a particular memory.  The desired error message is selected when the control circuit selects the memory.  In paragraph [0029]: “Such high speed communication may be desirable in situations where device 300 is about to completely fail and the error message in second memory 316 needs to be selected before failure”.  In other words, one can provide the desired error message without having to write the message to memory in the limited time in a failure situation.

Why might such a system be advantageous?  The outlined RFID circuit operates like a kind of tag that is in this case connected to and communicates with the circuitry of the electronic device.  Now the memory of a tag is commonly EEPROM, which is non-volatile and cheap.  This works well in situations where one simply wants to read data from the tag.  However EEPROM has very slow writes and has a limited write endurance.  In the case of a device failure there may not be sufficient time to write the error message to EEPROM.  Thus one would want a way around this slow write speed.

So what about the embodiment presented in Fig. 5?  It contains rewritable memory 512.  In paragraph [0033]: “… memory 512 may store information written thereto by control circuit 520”.  Other comments about memory 512 include “ … may store any information suitable for being provided as a message by RFID circuit 510…”, “… memory 512 may store error messages and various software events…”, and in paragraph [0036] “… memory 512 of RFID circuitry 510 provides limitless opportunity to communicate messages of varying specificity…” and “Other information such as the software event information may be updated at predetermined time intervals by writing updated data to memory 512 …”.   This sure does not sound like performance requirements EEPROM could meet.  Is it possible for another type of memory to meet the described performance?  FRAM comes to mind.

‘575 does not mention many of the hardware details, including the nature of the RFID memory associated with the various embodiments.  It appears to be directed more towards implementations of RFID circuits and their uses.   However, if the rewritable memory 512 still has to meet the requirement of writing an error message prior to device failure it is probably advisable to be a memory other than EEPROM.  Else, it has to be a really short message.

Sometimes a witty title is just too good to resist.  “Coming Soon: Superman’s Memory Crystals” is a case in point. If you are lucky, such a title is not an isolated piece of insight and you will advance some corner of knowledge after reading the article.  If you are unlucky, which is more often the case, the article has a large “entertainment” component and you struggle to the end.  Your “click” now simply adds you to the ranks of eyes for advertising.

Where does Superman’s memory fit?  The short answer is the core scientific development is quite interesting and deserves respect.  Unfortunately, it is masked by an overabundance of jargon and at least one premature extrapolation.  The long answer is that a lot could be accomplished with the information in the subject article and the cited references yet is left unrealized.

As illustrated schematically below there are three cited references, with the “root” being an article in Applied Physics Letters (APL).

It immediately strikes the reader that there is too much jargon in the article and references.  This jargon includes “whirlpools of polarized light”, “voxel”, “vortex drives”.  In the Southampton press release one finds the phrases “whirlpools of light that can be read much the came way as data in optical fibers” and “five-dimensional memory”.  Unfortunately we are not told what is occurring behind the jargon, including what the five dimensions are or how they apply to memory.  It certainly is not obvious.

The use of jargon such as “voxel” in the original APL paper is quite fine as the audience would likely have a background in the area and will understand the terminology.  However this can not be said for the other articles that are directed to a more general audience.  There should be another way of looking at this development.

So what does it all mean? Can we gain any understanding from these articles, ignoring the jargon and extrapolations? The answer is yes.  Moving forward we will consider only the information in the articles and see what can be extracted.

More to come.

Part II – superman’s quagmire: remaining questions
Part III – piecing something together

A while back there was a flurry of articles discussing Intel’s 3D Tri-gate and 3D technology involving the use of multiple layers of transistors, not just the single layer used today.  This “conversation” appeared to have origins around this discussion of the possible use of FinFET transistors, such as Intel’s Tri-gate at nodes below 20 nm.  While there was some interesting stuff in the earlier articles the discussion become a bit frayed around the edges towards the end.  This article in Computerworld even threw Multi-Chip Packaging technology into the fray.  In the end it appeared this thread had run its course.

Then this article, highlighting the comments of Morgan Stanley analyst Atif Malik, appeared in Barron’s on Monday.  The Barron’s article mentions “Intel is leading the way to three-dimensional chip structures” and “Malik expects foundries such as Taiwan Semiconductor Manufacturing and others to quickly follow Intel into 3D circuitry”.

As in many stories we have to go back before we can move forward.  The existing CMOS transistor paradigm could be generally described as two dimensional, where the channel, source and drain are all formed within the planar structure of the silicon wafer.  If you were able to look at a wafer after the formation of the above, yet prior to the formation of the gate structure, the substrate would be flat or planar.

Now, if you looked at a wafer destined for Tri-gate transistors, at roughly the same stage, you would see elongated rectangles on top of the silicon substrate.  In this case the channel, source and drain are all formed within these rectangles of silicon that rise above the planar substrate.  One might consider the transistor extends into the third dimension and voila 3D technology … or at least on the transistor level.  However, there is still a single layer of transistors and once the passivation is laid down on the finished transistors the chip structure is the same as current devices. Tri-gate is a transistor structure designed to address leakage problems at the 22 nm process node and below.  It is not a chip structure.

So to use a phrase from a old TV crime show, the name of which escapes me, “Let’s be careful out there”.

Cheaper High-Efficiency Solar Panels – is the title of this article out of Technology Review about two weeks ago.

Silicon wafers for use in solar panels require both the defect density and impurity levels are below low minimum values.  The low defect density is best achieved with single crystal wafers.  These are commonly produced by techniques that include the Czochralski single crystal growth process that is described in the article.  With regard to impurities the feedstock for a given single crystal growth technique has often undergone expensive purification processes, considerably adding to the cost of the final wafer and solar cell.

To reduce the costs associated with the crystal growth portion of wafer fabrication Suntech, as described in the article, is implementing a much simpler casting technique.  As discussed in the article Suntech has advanced upon a now public domain seed casting process.  Suntech’s improvements on this process reduce the amount of crystal nucleation naturally occurring along the crucible walls, a heterogeneous surface.  The result is a increased fraction of the ingot is a single grain allowing the overall ingot to approach a single crystal.  This discussion is certainly supported by the solar panel presented in the article’s figure.  There appear to be smaller grains grouped around the periphery of an individual cell of the panel, likely corresponding to the portion of ingot contacting the crucible.  A larger grain, which approaches a single crystal, lies roughly in the middle.  So far so good.

So what about the impurity level?  Will Suntech be using traditional feedstock for their casting process or will there be cost savings here as well?  This takes us back to Suntech’s October 19, 2010 press release, announcing the extension of their strategic partnership with Calisolar.  The release further discusses Suntech’s support for the addition of capacity to Calisolar’s 6N Silicon facility in Ontario.  6N Silicon was founded around a new technology for the purification of silicon for the solar industry. United States Patent 7,727,503 to Scott Nichol discloses at least aspects of the technology, which side-steps traditional purification techniques through a novel implementation of less expensive extractive metallurgy to at least largely meet the required purity levels.

To close the circle Suntech may be using silicon that has been purified with the techniques now owned by Calisolar for their casting process.  So my guess is that Canadian technology will be part of the cost reduction of the final solar panels.